The present invention relates to the fabrication of metal pillars in dielectrics, and more particularly to using polishing in the construction of spaced vertical metal pillars with planar tops and uniform heights either in and aligned with or extending above the dielectric layer of an electrical interconnect structure.
Current multi-chip circuitry design requires the attachment of numerous integrated circuit chips to high density electrical interconnects. The electrical interconnects normally include surface pads on a dielectric for bonding to surface mounted chips, and metal lines buried in the dielectric for electrically connecting selected pads. Frequently polyimide is used as the dielectric and copper is used as the metal. It is also common to stack up separate orthogonal layers of copper lines in the dielectric and to provide inter-layer connections (e.g. for lines-to-lines or lines-to-pads) by filling inter-layer holes or vias with a conductive metal. For instance, vertical inter-layer vias can be filled with copper, nickel or nickel alloys to form metal pillars in the dielectric. In such a structure the fabrication of metal pillars becomes a critical step in the overall construction of the electrical interconnect.
There are numerous techniques in the prior art for fabricating metal pillars in the dielectric of an electrical interconnect. Additive techniques include stacking up the pillars and then coating the pillars with a dielectric; whereas in substractive approaches a layer of dielectric is provided, vias are formed in the top of the dielectric and then metal is deposited into the vias. Methods of metallic deposition include electroless plating, electroplating, sputtering, and evaporation. Nevertheless., there is a continuing need to reduce process steps and lower fabrication costs.